Scope

As a part of the IEEE International green Computing conference, a special workshop on low power System on Chip (SoC) will be organized. This workshop will address various aspects of designing power efficient SoC and low power SoC test. The continuing progress in silicon technologies and integration levels is producing complete end-user systems on a single chip. Design technologies in this massive integration era will present unprecedented advantages and challenges, the former being related to very high device densities and the latter to soaring power dissipation issues. Reducing on-chip power consumption has become a critical issue for the ultra-deep submicron/nanotechnology regime. The traditional trade-off between performance and area is now being compounded by the addition of power into the equation. Design of a low-power SoC involves adopting various strategies at different levels of abstraction. Starting from overall architecture, choice of processors and memory blocks, target technology, I/O, place & route strategy, circuit design styles everything influence design of a power efficient SoC. Moreover, in the emerging multi-core SoC domain, roles of power efficient interconnects and data routing protocols are very important. Above all, the recent development of complex, high-performance, low-power devices implemented in deep-submicron technologies creates a new class of more sophisticated electronic products, which makes power management a critical parameter that test engineers cannot ignore during test development.

This workshop will encompass a broad range of topics related to low power SoC design and test. Its objective is to facilitate exchange of valuable information and ideas among a wide spectrum of researchers. The workshop will consist of invited presentations and contributed peer-reviewed research papers. The topics of interest include, but are not limited to, the following:

 

• Low power SoC architecture
• Low power processor design
• I/O design
• Clock routing
• Power efficient circuit design
• Low power memory design
• Low power and high frequency transceiver
• Energy efficient multi-core architectures and Network-on-Chip
• Emerging interconnect technologies, like on-chip photonic, RF and wireless interconnects.
• Low power coding methods for SoCs
• Low power SoC test

Author Information

Full papers following the guidelines of the International Green Computing Conference http://www.green-conf.org/call_papers.aspx are sought. All submitted manuscripts will be reviewed and evaluated on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the scope of the workshop. All the papers presented in this workshop will be published in the official conference proceedings (through IEEE Digital Library) is contingent on two conditions: (1) that at least one author of an accepted paper registers for the conference at the time of the submission of the final manuscript and (2) that one of the authors presents the paper at the workshop in person.

Submission Due: 22nd May 2010 
Notification of Acceptance: 15th June 2010
Camera ready paper due: 30th June 2010.

Please direct questions regarding this workshop to Partha Pande (pande@eecs.wsu.edu)